Should be strong in C++ & SystemC.Should be above average in VHDL or Verilog. Experience of TLM and AXI bus protocols and Mixed language simulation
Xilinx Company Official website: www.xilinx.com
JOB NAME: Junior ESL-Simulation Research Engineer
SAL: As per norms.
Place: All over india.
LAST DATE: As soon as possible.
EDU: B.E/B.Tech
Experience: Freshers or 0 to 24 months of expereince.
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